The researchers at IBM found a way to put a microscopic barrier between the copper and silicon in a way that actually reduced the number of steps needed to complete a chip. With this development, IBM is able to produce extremely intricate circuit designs with copper at widths of 0.20 microns -- down from the current industry standard of 0.25 microns.
IBM has christened the manufacturing process CMOS 7S. CMOS 7S has the ability to reduce manufacturing scales to 0.15 and even 0.10 micron. As a result, designers will now be able to pack between 150 million and 200 million transistors on a single chip.
Fig. 1 Scanning Electron Microscope image of a six layer copper process.
In CMOS 7S, IBM turned to a technique known as damascene processing to overcome this problem of copper migration. The position of the copper track required is first marked out on the silicon wafer with a liner material, forming an open channel. The copper is then deposited into the channel, which isolates the copper from the silicon and prevents it from migrating. The copper channel is then capped on the top by yet another material.
The process adds a number of complicated steps to the traditional chip manufacturing process. In addition to copper interconnects, CMOS 7S transistors also boast a 0.12 micron effective channel length, the shortest publicly reported in the industry. Channel length is the distance current must travel through a transistor in semiconductor circuits; so shorter channel length ultimately results in faster switching and better performance.