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DualDDR at a glance
By: Kevin Young, February 12, 2003  Print this article


I am sure there are many of you that have heard of, but aren’t sure about what DualDDR is, so let’s spend a moment to give you a brief introduction to the technology.

Your typical memory bus today is 64-bits. However, the nForce2 Platform Processors utilize a new and higher performance 128-bit (effective) memory bus, theoretically capable of delivering 100% more peak bandwidth.

Based upon the first-generation nForce Platform Processors, NVIDIA’s DualDDR design again employs two 64-bit memory controllers, providing an effective 128 bit memory interface, while utilizing new proprietary algorithms for pre-fetching and pre-processing memory requests.

Lowest Latency

More than just a single “128-bit” memory controller, DualDDR consists of two independent, complementary, and intelligent memory controllers. Both memory controllers operate concurrently to each other to “hide” latencies associated with typical “chipsets”. For example, controller “A” reads or writes to main memory while the controller “B” prepares for the next access, and vice versa. The complementary nature of the two memory controllers cuts the effective latency in half.

Equally important is the second-generation dynamic adaptive speculative pre-processor (DASP), which has been re-architect with a more aggressive algorithm. Write buffers and draining algorithms has also been re-architected to reduce latency.

To sum it up, the nForce2 utilize two 64-bit memory controllers, providing a 128 bit effective memory interface and more aggressive timings to reduce latency, boosting the performance by 100% over the typical 64-bit DIMMs. In addition, DualDDR also doubles the addressable memory space to 3GB.

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